Depleted Substrate Transistor—Single Gate

One of the ways to overcome the issue of static power is to increase the threshold voltage. However, increasing the threshold voltage while scaling the power-supply voltage decreases the drive current of the device. A feasible way of addressing the power issue is to improve the sub-threshold gradient of the transistor. As the transistor scales, and the channel doping increases to support the thinner oxide, the sub-threshold gradient degrades. The sub-threshold gradient is linked to the depletion capacitance by the equation

S=(kT/q).1n10.(1+C_D/C_ox)      [4]

where T is the temperature, q is the electronic charge, S is the sub-threshold gradient, CD is the capacitance of the depletion region, and C_ox is the gate-oxide capacitance [9]. From equation 4, it can be seen that decreasing the depletion capacitance C_d will improve the sub-threshold gradient towards the minimum theoretical value of 60mV/decade. Decreasing C_D can be achieved by the use of Silicon-On-Insulator with a fully depleted substrate, since the depletion layer now extends through the buried oxide into the substrate. The value of C_D then becomes negligible compared to C_ox in Equation 4. We call this broad category of devices, which include several elements necessary for future scaling, a Depleted Substrate Transistor (DST), and this can be seen in Figure 21 [10].

Figure 21: Illustration of Depleted Substrate Transistor (DST)

We define the DST as consisting of three elements:

• The body of the device is fully depleted, be this double-gate (DG) [9] transistors, gate-all-around transistors (GAA) [11], or even transistors whose bodies are no longer silicon (III-V's etc.).
   
• The gate dielectric is a high-k material mentioned previously.
   
• The junctions are raised epitaxial source/drain.
   

Figure 22 shows a TEM cross section of such a device. The epitaxial raised source/drain are necessary to decrease the series resistance of the transistor, due to the thin silicon body.

Figure 22: TEM of the Depleted Substrate Transistor (DST)

Depleted Substrate CMOS transistors were fabricated on a thin silicon body with a thickness of <25nm on top of a ~200nm buried oxide. The physical gate-oxide thickness was equal to 1.5nm, the same as the bulk devices. Figure 23 shows the I_d-V_g characteristics of two 60nm L_g n-MOS transistors, a bulk transistor and a DST.

Figure 23: Log Id-V_g characteristics of a bulk and DST transistor

Two features can be seen from this figure: the sub-threshold gradient, which has improved from 95 mV/decade to 75mV/decade, and the DIBL, which has decreased from 100mV/V to 45 mV/V. The improved sub-threshold gradient thus allows the DST to decrease threshold voltage by 40-50mV, while the improvement in DIBL allows a further 50mV decrease in V_t. As power supply voltages decrease below 1V, the DST devices will allow substantial gains in gate overdrive (V_g-V_t), as well a reduction in off-state power by 2 orders of magnitude.

Depleted Substrate Transistor—Double Gate

As transistors continue to scale, control of short channel effects become more and more important. It will be increasingly difficult to control the electrostatic communication between source and drain that results in transistor leakage by using bulk or even single-gate DSTs. Solutions are being researched that enclose the channel area by the gate stack. The most common form of this transistor architecture is called the Double-Gate transistor.

Figure 24 shows an illustration of a two-fin transistor, one form of double-gate device. In this case, the current runs along both sidewalls of the fins.

Figure 24: Illustration of a two-FinFET Double-Gate transistor. The current flows along each sidewall of the fins

The gate controls the front and back of such a double-gate transistor, thus offering better short channel control than a single gate. However, double-gate devices are much more difficult to fabricate due to their three-dimensional nature. Figure 25 shows a double-gate FinFET device in the direction of current flow and Figure 26 shows the transistor perpendicular to current flow.

Figure 25: SEM of Double-Gate Multi-Fin Structure

Figure 26: TEM cross-section of a 30nm double-gate device

In terms of short channel control, simulations have shown that double-gate devices can buy up to a two-generational gain in DIBL over single-gate DSTs [12]. However, it should be noted that one of the issues concerning both types of device is the thickness of the silicon that forms the channel region. In the case of single-gate DSTs, the thickness of the silicon channel body has been found to be approx L_g/3. In the case of double-gate DSTs, the thickness of the Fin is twice the body thickness (2L_g/3), as each gate controls a thickness of L_g/3.

As the gate length scales, the thickness of the silicon body (Tsi) also scales. Figure 27 shows the thicknesses needed to provide full depletion for both single- and double-gate DSTs. It can be seen that for single gates, the thickness quickly approaches to less than 10nm. This constraint of requiring Tsi < 10nm is relaxed in FinFETs, since the Tsi is perpendicular to the wafer plane (Figure 24), and the thickness values are twice that of single-gate DSTs (Tsi is the fin width in the case of double-gates). However, this dimension is achieved using lithography, and this means that the most critical lithography step is no longer polysilicon patterning, but Fin patterning. In other words, for FinFET devices, the fin width needs to be smaller than the gate length. For example, for 20nm L_gs, the Fin patterning will require lithography that can reproducibly print 13nm Fin widths.

Figure 27: Silicon body thickness required for full depletion of a single-gate DST and a double-gate DST

Drive Current

One of the most serious issues with gate length scaling is our ability to maintain high drain current as the power-supply voltage scales without being able to fully scale V_t, which remains high to control transistor leakage currents. The power-supply scaling shown in Figure 1 suggests that keeping Idsat constant will be a significant challenge. In order to illustrate this point, Figure 28 shows the data from a 20nm gate length device at Vdd=0.85V and Vdd=0.7V. It can be seen that a power-supply voltage drop of 0.15V results in a drop of 30% in the drive current capabilities of the transistor, from 533 mA/mm to 375 mA/mm. Some of the issues facing drive current scaling are discussed below.

Figure 28: Id-Vd characteristics for the 20nm transistor at two different supply voltages, 0.85V and 0.7V

Series Resistance

With DST-like devices comes the need to keep the body thickness in the range that allows for complete depletion. In the representation of the DST transistor in Figure 21, the thickness of the silicon body (T_Si) needs to be kept to around L_g/3 to maintain complete depletion (see also Figure 27). As the transistors scale to L_g=20nm, the body thickness will need to be of the order of 6-7nm. Apart from the fabrication issues for such thin bodies discussed above, the increase in series resistance arising from ultra-thin junctions will limit transistor drive currents [13].

The solution to the drive current issue (from external parasitic resistance) is to use raised source/drain, which increases the effective thickness of the junctions and hence the junction conductance [14]. Figure 29 shows the advantage of raised source/drains over conventional junctions on DST transistors. The transistors with and without raised source/drain were fabricated with a gate length of 60nm. At matched I_off of 60nA/mm, DST devices with raised source/drain (blue lines) exhibit superior drive currents, up to 50% more than the non-raised source/drain DST structures (red lines).

Figure 29: I_D-V_D characteristics for 60nm DST transistors, with no raised S/D (red lines), and with raised S/D (blue lines)

Figure 30 further illustrates the performance gains that can be obtained in combining DST with raised source/drains. Figure 30 shows the PMOS I_on-I_off comparison of the depleted-substrate transistor with and without raised source/drain, and the standard 0.13um-generation bulk Si transistors at V_d = 1.3V. For a given I_off (e.g., 1.0 nA/um), the depleted-substrate transistor with raised source/drain shows the highest I_on value, about 30% higher than the standard bulk Si transistor. Conversely, at a fixed drive current (e.g., at 0.6mA/mm), the off-current is decreased by about two orders of magnitude for DST.

Figure 30: Comparson of p-MOS bulk silicon (triangles), DST (circles) and DST with raised source/drains (squares)

Another way of looking at the data is from a power-supply perspective. DST pMOS with raised source/drain achieves the same I_on-I_off performance at 1.1V as the bulk-device at 1.3V, thus enabling a reduction in power by 30% (power a voltage²).